Embedded electronic control systems incorporate serial communications between a controller, subsystem components, peripherals, and other controllers. Serial communication systems may be inexpensive, function reliably, and ease introduction of new technologies when used within an environment incorporating appropriate standards. A protocol, known as a local interconnect network (LIN) bus is one example of a serial communications standard meeting the requirements of an electronic control system.
With reference to FIG. 1, a prior art microcontroller architecture 100 incorporates a LIN controller 109. A microprocessor core 190 is connected by an address bus 110 and a read/write select line (R/W) 113 to an on-chip memory 105, a timer 106, an external bus interface (EBI) 103, and a universal asynchronous receiver/transmitter (UART) 107. The address bus 110 also connects to an address decoder 101. A write bus 111 connects from an output of the microprocessor core 190 to the on-chip memory 105, the timer 106, the EBI 103, and the UART 107. A read bus 112 connects from an output of a data mux 104 to an input of the microprocessor core 190. An on-chip memory read bus 121 connects from the on-chip memory 105, a timer read bus 122 connects from the timer 106, an external interface read bus 120 connects from the EBI 103, and a UART read bus 123 connects from the UART 107 each connect to a separate input of the data mux 104.
The address decoder 101 produces at most one of four different select signals on one of four respective select lines. The four select lines are an on-chip memory select line 131 connecting to the on-chip memory 105, a timer select line 132 connecting to the timer 106, an external bus interface select line 130 connecting to the EBI 103, and a UART select line 133 connecting to the UART 107. Each of the four select lines also connects to the data mux 104. An interrupt controller 102 connects to a timer interrupt line 142 from the timer 106 and to a UART interrupt line 143 coming from the UART 107. The interrupt controller 102 connects to the microprocessor core 190 through a processor interrupt line 140. At the UART 107, a transmit data line TXD and a receive data line RXD connect to and from a LIN transceiver 108 respectively. A bidirectional serial LIN bus 181 connects to the LIN transceiver 108.
With reference to FIG. 2, a UART frame 200 commences with a start bit transitioning from a high logic level (VDD) to a low logic level (GND). The start bit is followed by eight data bits B0-B7 and a stop bit. Each one of the UART frame bits is one bit period (a Tbit) long.
With reference to FIG. 3 a prior art LIN controller 109 (FIG. 1) connects through a bidirectional microcontroller peripheral bus 350 to the microprocessor core 190 (FIG. 1). A clock line 353 connects to a LIN user interface 304, a LIN transmitter 301, a LIN receiver 303, and a baud rate generator 302. The LIN user interface 304 contains an identifier register (IDR) 306, a transmit hold register (THR) 308, a mode register (MODE) 310, a control register (CTRL) 312, a receive hold register (RHR) 316, and a status register 314 containing two synchronization flags. The synchronization flag signals in the status register 314 are a transmit ready flag TXRDY and a receive ready flag RXRDY.
The LIN transmitter 301 contains a 3-to-1 multiplexer 321 that connects to the identifier register 306, the transmit hold register 308, and a checksum generator 323. An output of the 3-to-1 multiplexer 321 connects to the checksum generator 323 and a transmit shift register 325. The transmit shift register 325 connects to the transmit data line TXD (FIG. 1). A transmit FSM (finite state machine) 327 connects to the identifier register 306, the checksum generator 323, the transmit shift register 325, the transmit ready flag TXRDY in the status register 314, the mode register 310, the control register 312, and the baud rate generator 302.
The LIN receiver 303 contains a receive shift register 335 connected to the receive data line RXD (FIG. 1), the receive hold register 316, and a checksum check block 333. A receive FSM (finite state machine) 337 connects to the checksum check block 333, the receive shift register 335, the receive ready flag RXRDY, the mode register 310, the control register 312, and the baud rate generator 302.
A LIN controller 109 (FIG. 1) may be configured as a master or as a slave. On a LIN bus, several LIN controllers 109 may be connected but only one may be acting as a master while all others controllers are connected as slaves. The master initiates communication by sending a header. In response to the header a master or one of the slaves sends a response.
With reference to FIG. 4, a LIN frame 405 is composed of multiple UART frames 200 and is classified as a UART multiframe. The LIN frame 405 is made up of a header 410 and a response 415, each of which is a UART multiframe. The header 410 is composed of a break field 420, a sync field 425, and an identifier field 430. The break field 420 is defined by the bus signal transitioning from high to low and maintaining a logic low level for a minimum duration of 13 Tbits long. The sync field 425 is a specific pattern (the data value 0×55), which causes regular toggling of the serial bus and is used to synchronize the slaves baud rate compared to the master. Sending of the sync field 425 sets an example of a typical expected time between two rising edges of any transmission. A break field 420 begins any LIN frame 405. The identifier field 430 contains a message identifier (not shown) incorporating information about the transmitter, the receiver(s), the purpose of the LIN frame 405, and a data field length (not shown). The response 415 is composed of 1 to N data fields 444a, . . . , 444g, 444h followed by a checksum field 450. The data field length (N) may typically be 1, 2, 4, or 8 data fields long.
With reference to FIG. 5, the LIN controller 109 (FIG. 1), configured as a master, sends the header 410 and sends the response 415 of the LIN frame 405. The microprocessor core 190 signals commencement of loading the identifier field 430 into the identifier register 306 by initiating a WRITE_IDENTIFIER_REGISTER command 515. The header 410 is initiated for transmission by sending the break field 420 and the synch field 425. The identifier field 430 contains information identifying transmission of the response field 415. The Receipt of the WRITE_IDENTIFIER_REGISTER command 515 triggers the transmit FSM 327 (FIG. 3) to lower the transmit ready flag TXRDY 555, select the identifier register 306 with the 3-to-1 multiplexer 321, and shift the identifier field 430 to the transmit shift register 325. As the LIN controller 109 sends the response 415, a raised transmit ready flag 540a is produced as the identifier field 430 starts transmission over the transmit data line TXD.
The transmit ready flag TXRDY rising signals the microprocessor core 190 that a next field may be written to the transmit hold register 308. The microprocessor core 190 places a first data field 444a in the transmit hold register 308 and initiates a first WRITE_THR command 565a. The first WRITE_THR command 565a causes the transmit FSM 327 to select the transmit hold register 308 with the 3-to-1 multiplexer 321 and write the first data field 444a to the transmit shift register 325. The transmit ready flag TXRDY lowers 545a at commencement of the first WRITE_THR command 565a corresponding to the first data field 444a. 
A second raised transmit ready flag 540b occurs when the first data field 444a has been written to the transmit shift register 325 and is ready for transmission over the transmit data line TXD to the LIN transceiver 108 (FIG. 1). Corresponding sequences of raised transmit ready flags 540a, 540b, . . . , 540g, 540h; WRITE_THR commands 565a, 565b, . . . , 565g, 565h; lowered transmit ready flags 545a, 545b, . . . , 545g, 545h; and sent data fields 444a, . . . , 444g, 444h occur as explained (in the singular), supra, until an entire response 415 is transmitted. The identifier field 430 contains information to indicate to the transmit FSM 327 how many data fields there are to send.
After the last data field 444h is sent, the transmit FSM 327 enters a generate_checksum state (not shown) causing selection of the checksum generator 323 by the 3-to-1 multiplexer 321 and writing of a checksum field 450 to the transmit shift register 325. The checksum generator 323 maintains a checksum during transmission of the sequence of data fields 444a, . . . , 444g, 444h. After the checksum field 450 is transmitted, the transmit ready flag TXRDY is raised 559 by the transmit FSM 327 signifying the end of the LIN frame 405.
With reference to FIG. 6, the LIN controller 109 (FIG. 1), configured as a master, sends the header 410 and receives the response 415 of the LIN frame 405. The microprocessor core 190 signals commencement of loading the identifier field 430 into the identifier register 306 by initiating a WRITE_IDENTIFIER_REGISTER command 515. The header 410 is initiated for transmission by sending the break field 420a and the synch field 425. The identifier field 430 contains information identifying characteristics of the response field 415. The Receipt of the WRITE_IDENTIFIER_REGISTER command 515 triggers the transmit FSM 327 (FIG. 3) to lower the transmit ready flag TXRDY 555a, select the identifier register 306 with the 3-to-1 multiplexer 321, and shift the identifier field 430 to the transmit shift register 325. In the case of the LIN controller 109 receiving the response 415, the transmit ready flag TXRDY remains at a low logic level until the end of the LIN frame 405.
Another LIN controller 109 (FIG. 1), configured as a slave, responds to the header 410 by sending a first data field 444a over the LIN bus, through the LIN transceiver 108 of the LIN controller 109 configured as a master, and over the receive data line RXD. After the first data field 444a is completely read into the receive shift register 335 (FIG. 3) and transferred into the receive hold register 316, the receive FSM 337 causes a raised receive ready flag 640a. The high logic level of the receive ready flag RXRDY signals the microprocessor core 190 that the first data field 444a is ready for reading. The microprocessor core 190 issues a first READ_RHR command 656a that transfers the first data field 444a and causes the receive FSM 337 to lower the receive ready flag 645a. 
The receive shift register 335 of the LIN (master) controller 109 (FIG. 1) receives a sequence of data fields 444a, . . . , 444g, 444h from the targeted (slave) LIN controller 109. Correspondingly, a sequence of data fields 444a, . . . , 444g, 444h; a sequence of raised receive ready flags 640a, . . . , 640f, 640g, 640h; a sequence of READ_RHR commands 656a, . . . , 656f, 656g, 656h; and a sequence of lowered receive ready flags 645a, . . . , 645f, 645g, 645h occur as explained (in the singular) supra, until an entire response 415 is received.
After the last data field 444h is received, the receive FSM 337 of the (master) LIN controller 109 (FIG. 1) enters a check_checksum state (not shown) causing receipt of the last field as a checksum field 450. The checksum check block 333 maintains a checksum during receipt of the sequence of data fields 444a, . . . , 444g, 444h. Comparison of the maintained checksum with the checksum field 450 is made. On a comparison indicating equal values for the maintained checksum and the checksum field 450, a raised transmit ready flag 559 signifies the end of the LIN frame 405. On a non-equal comparison of checksums, a transmission error is forwarded to the microprocessor core 190.
The microprocessor core 190 is directly involved in details regarding determination of a minimum LIN frame time slot (not shown) and programming of the timer 106. The microprocessor core 190 has significant overhead in servicing and resetting of interrupts from the timer 106, the UART 107, the LIN controller 109 (FIG. 1), and the remainder of the embedded electronic control system. The resources of the system involved in timing and managing minimum LIN frame time slot details are not available to manage other applications the system is called on to handle. In addition, interrupts from the remainder of the system may vie for handling by service routines executed by the microprocessor core 190. The additional interrupt servicing keeps the microprocessor core 190 from properly managing all of the interrupts concurrently with other system resource requirements within the time limits of the minimum LIN frame time slot. Failure of the microprocessor core 190 to properly manage interrupts and system resources during a minimum LIN frame time slot, means the LIN controller 109 operating as the master is out of compliance with the LIN protocol and system communications are erroneous.
It would be desirable to determine the duration of a minimum LIN frame time slot, timer operations, and appropriate interrupts in compliance with the LIN protocol and not require direct involvement of the microprocessor core 190 and general system resources in providing timing details for minimum LIN frame time slot. It is desirable for the appropriate protocol management to be done by an interface device, which offloads the microprocessor core 190 from the minutia of the commands, interrupts, and certain service routines that comprise a monopolizing overhead of system resources.